MySensors Library & Examples
2.3.2
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The values here are designed to be passed to various functions in the bcm2835 library.
Macros | |
#define | HIGH 0x1 |
#define | LOW 0x0 |
#define | MIN(a, b) (a < b ? a : b) |
#define | BCM2835_CORE_CLK_HZ 250000000 |
#define | BMC2835_RPI2_DT_FILENAME "/proc/device-tree/soc/ranges" |
#define | BCM2835_PERI_BASE 0x20000000 |
#define | BCM2835_PERI_SIZE 0x01000000 |
#define | BCM2835_RPI2_PERI_BASE 0x3F000000 |
#define | BCM2835_RPI4_PERI_BASE 0xFE000000 |
#define | BCM2835_RPI4_PERI_SIZE 0x01800000 |
#define | BCM2835_ST_BASE 0x3000 |
#define | BCM2835_GPIO_PADS 0x100000 |
#define | BCM2835_CLOCK_BASE 0x101000 |
#define | BCM2835_GPIO_BASE 0x200000 |
#define | BCM2835_SPI0_BASE 0x204000 |
#define | BCM2835_BSC0_BASE 0x205000 |
#define | BCM2835_GPIO_PWM 0x20C000 |
#define | BCM2835_AUX_BASE 0x215000 |
#define | BCM2835_SPI1_BASE 0x215080 |
#define | BCM2835_SPI2_BASE 0x2150C0 |
#define | BCM2835_BSC1_BASE 0x804000 |
#define | BCM2835_PAGE_SIZE (4*1024) |
#define | BCM2835_BLOCK_SIZE (4*1024) |
#define | BCM2835_GPFSEL0 0x0000 |
#define | BCM2835_GPFSEL1 0x0004 |
#define | BCM2835_GPFSEL2 0x0008 |
#define | BCM2835_GPFSEL3 0x000c |
#define | BCM2835_GPFSEL4 0x0010 |
#define | BCM2835_GPFSEL5 0x0014 |
#define | BCM2835_GPSET0 0x001c |
#define | BCM2835_GPSET1 0x0020 |
#define | BCM2835_GPCLR0 0x0028 |
#define | BCM2835_GPCLR1 0x002c |
#define | BCM2835_GPLEV0 0x0034 |
#define | BCM2835_GPLEV1 0x0038 |
#define | BCM2835_GPEDS0 0x0040 |
#define | BCM2835_GPEDS1 0x0044 |
#define | BCM2835_GPREN0 0x004c |
#define | BCM2835_GPREN1 0x0050 |
#define | BCM2835_GPFEN0 0x0058 |
#define | BCM2835_GPFEN1 0x005c |
#define | BCM2835_GPHEN0 0x0064 |
#define | BCM2835_GPHEN1 0x0068 |
#define | BCM2835_GPLEN0 0x0070 |
#define | BCM2835_GPLEN1 0x0074 |
#define | BCM2835_GPAREN0 0x007c |
#define | BCM2835_GPAREN1 0x0080 |
#define | BCM2835_GPAFEN0 0x0088 |
#define | BCM2835_GPAFEN1 0x008c |
#define | BCM2835_GPPUD 0x0094 |
#define | BCM2835_GPPUDCLK0 0x0098 |
#define | BCM2835_GPPUDCLK1 0x009c |
#define | BCM2835_GPPUPPDN0 0x00e4 /* Pin pull-up/down for pins 15:0 */ |
#define | BCM2835_GPPUPPDN1 0x00e8 /* Pin pull-up/down for pins 31:16 */ |
#define | BCM2835_GPPUPPDN2 0x00ec /* Pin pull-up/down for pins 47:32 */ |
#define | BCM2835_GPPUPPDN3 0x00f0 /* Pin pull-up/down for pins 57:48 */ |
#define | BCM2835_GPIO_PUD_ERROR 0x08 |
#define | BCM2835_PADS_GPIO_0_27 0x002c |
#define | BCM2835_PADS_GPIO_28_45 0x0030 |
#define | BCM2835_PADS_GPIO_46_53 0x0034 |
#define | BCM2835_PAD_PASSWRD (0x5A << 24) |
#define | BCM2835_PAD_SLEW_RATE_UNLIMITED 0x10 |
#define | BCM2835_PAD_HYSTERESIS_ENABLED 0x08 |
#define | BCM2835_PAD_DRIVE_2mA 0x00 |
#define | BCM2835_PAD_DRIVE_4mA 0x01 |
#define | BCM2835_PAD_DRIVE_6mA 0x02 |
#define | BCM2835_PAD_DRIVE_8mA 0x03 |
#define | BCM2835_PAD_DRIVE_10mA 0x04 |
#define | BCM2835_PAD_DRIVE_12mA 0x05 |
#define | BCM2835_PAD_DRIVE_14mA 0x06 |
#define | BCM2835_PAD_DRIVE_16mA 0x07 |
#define | BCM2835_AUX_IRQ 0x0000 |
#define | BCM2835_AUX_ENABLE 0x0004 |
#define | BCM2835_AUX_ENABLE_UART1 0x01 |
#define | BCM2835_AUX_ENABLE_SPI0 0x02 |
#define | BCM2835_AUX_ENABLE_SPI1 0x04 |
#define | BCM2835_AUX_SPI_CNTL0 0x0000 |
#define | BCM2835_AUX_SPI_CNTL1 0x0004 |
#define | BCM2835_AUX_SPI_STAT 0x0008 |
#define | BCM2835_AUX_SPI_PEEK 0x000C |
#define | BCM2835_AUX_SPI_IO 0x0020 |
#define | BCM2835_AUX_SPI_TXHOLD 0x0030 |
#define | BCM2835_AUX_SPI_CLOCK_MIN 30500 |
#define | BCM2835_AUX_SPI_CLOCK_MAX 125000000 |
#define | BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 |
#define | BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF |
#define | BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 |
#define | BCM2835_AUX_SPI_CNTL0_CS0_N 0x000C0000 |
#define | BCM2835_AUX_SPI_CNTL0_CS1_N 0x000A0000 |
#define | BCM2835_AUX_SPI_CNTL0_CS2_N 0x00060000 |
#define | BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 |
#define | BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 |
#define | BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 |
#define | BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 |
#define | BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 |
#define | BCM2835_AUX_SPI_CNTL0_CPHA_IN 0x00000400 |
#define | BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 |
#define | BCM2835_AUX_SPI_CNTL0_CPHA_OUT 0x00000100 |
#define | BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 |
#define | BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 |
#define | BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F |
#define | BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 |
#define | BCM2835_AUX_SPI_CNTL1_IDLE 0x00000080 |
#define | BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000040 |
#define | BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 |
#define | BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 |
#define | BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000 |
#define | BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000 |
#define | BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 |
#define | BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 |
#define | BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 |
#define | BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 |
#define | BCM2835_AUX_SPI_STAT_BUSY 0x00000040 |
#define | BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F |
#define | BCM2835_SPI0_CS 0x0000 |
#define | BCM2835_SPI0_FIFO 0x0004 |
#define | BCM2835_SPI0_CLK 0x0008 |
#define | BCM2835_SPI0_DLEN 0x000c |
#define | BCM2835_SPI0_LTOH 0x0010 |
#define | BCM2835_SPI0_DC 0x0014 |
#define | BCM2835_SPI0_CS_LEN_LONG 0x02000000 |
#define | BCM2835_SPI0_CS_DMA_LEN 0x01000000 |
#define | BCM2835_SPI0_CS_CSPOL2 0x00800000 |
#define | BCM2835_SPI0_CS_CSPOL1 0x00400000 |
#define | BCM2835_SPI0_CS_CSPOL0 0x00200000 |
#define | BCM2835_SPI0_CS_RXF 0x00100000 |
#define | BCM2835_SPI0_CS_RXR 0x00080000 |
#define | BCM2835_SPI0_CS_TXD 0x00040000 |
#define | BCM2835_SPI0_CS_RXD 0x00020000 |
#define | BCM2835_SPI0_CS_DONE 0x00010000 |
#define | BCM2835_SPI0_CS_TE_EN 0x00008000 |
#define | BCM2835_SPI0_CS_LMONO 0x00004000 |
#define | BCM2835_SPI0_CS_LEN 0x00002000 |
#define | BCM2835_SPI0_CS_REN 0x00001000 |
#define | BCM2835_SPI0_CS_ADCS 0x00000800 |
#define | BCM2835_SPI0_CS_INTR 0x00000400 |
#define | BCM2835_SPI0_CS_INTD 0x00000200 |
#define | BCM2835_SPI0_CS_DMAEN 0x00000100 |
#define | BCM2835_SPI0_CS_TA 0x00000080 |
#define | BCM2835_SPI0_CS_CSPOL 0x00000040 |
#define | BCM2835_SPI0_CS_CLEAR 0x00000030 |
#define | BCM2835_SPI0_CS_CLEAR_RX 0x00000020 |
#define | BCM2835_SPI0_CS_CLEAR_TX 0x00000010 |
#define | BCM2835_SPI0_CS_CPOL 0x00000008 |
#define | BCM2835_SPI0_CS_CPHA 0x00000004 |
#define | BCM2835_SPI0_CS_CS 0x00000003 |
#define | BCM2835_BSC_C 0x0000 |
#define | BCM2835_BSC_S 0x0004 |
#define | BCM2835_BSC_DLEN 0x0008 |
#define | BCM2835_BSC_A 0x000c |
#define | BCM2835_BSC_FIFO 0x0010 |
#define | BCM2835_BSC_DIV 0x0014 |
#define | BCM2835_BSC_DEL 0x0018 |
#define | BCM2835_BSC_CLKT 0x001c |
#define | BCM2835_BSC_C_I2CEN 0x00008000 |
#define | BCM2835_BSC_C_INTR 0x00000400 |
#define | BCM2835_BSC_C_INTT 0x00000200 |
#define | BCM2835_BSC_C_INTD 0x00000100 |
#define | BCM2835_BSC_C_ST 0x00000080 |
#define | BCM2835_BSC_C_CLEAR_1 0x00000020 |
#define | BCM2835_BSC_C_CLEAR_2 0x00000010 |
#define | BCM2835_BSC_C_READ 0x00000001 |
#define | BCM2835_BSC_S_CLKT 0x00000200 |
#define | BCM2835_BSC_S_ERR 0x00000100 |
#define | BCM2835_BSC_S_RXF 0x00000080 |
#define | BCM2835_BSC_S_TXE 0x00000040 |
#define | BCM2835_BSC_S_RXD 0x00000020 |
#define | BCM2835_BSC_S_TXD 0x00000010 |
#define | BCM2835_BSC_S_RXR 0x00000008 |
#define | BCM2835_BSC_S_TXW 0x00000004 |
#define | BCM2835_BSC_S_DONE 0x00000002 |
#define | BCM2835_BSC_S_TA 0x00000001 |
#define | BCM2835_BSC_FIFO_SIZE 16 |
#define | BCM2835_ST_CS 0x0000 |
#define | BCM2835_ST_CLO 0x0004 |
#define | BCM2835_ST_CHI 0x0008 |
Variables | |
uint32_t * | bcm2835_peripherals_base |
uint32_t | bcm2835_peripherals_size |
uint32_t * | bcm2835_peripherals |
volatile uint32_t * | bcm2835_st |
volatile uint32_t * | bcm2835_gpio |
volatile uint32_t * | bcm2835_pwm |
volatile uint32_t * | bcm2835_clk |
volatile uint32_t * | bcm2835_pads |
volatile uint32_t * | bcm2835_spi0 |
volatile uint32_t * | bcm2835_bsc0 |
volatile uint32_t * | bcm2835_bsc1 |
volatile uint32_t * | bcm2835_aux |
volatile uint32_t * | bcm2835_spi1 |
#define BCM2835_AUX_BASE 0x215000 |
#define BCM2835_AUX_ENABLE_SPI0 0x02 |
#define BCM2835_AUX_ENABLE_SPI1 0x04 |
#define BCM2835_AUX_SPI_PEEK 0x000C |
#define BCM2835_AUX_SPI_TXHOLD 0x0030 |
#define BCM2835_BLOCK_SIZE (4*1024) |
#define BCM2835_BSC0_BASE 0x205000 |
#define BCM2835_BSC1_BASE 0x804000 |
#define BCM2835_BSC_C_CLEAR_1 0x00000020 |
#define BCM2835_BSC_C_CLEAR_2 0x00000010 |
#define BCM2835_BSC_C_I2CEN 0x00008000 |
#define BCM2835_BSC_C_ST 0x00000080 |
#define BCM2835_BSC_CLKT 0x001c |
#define BCM2835_BSC_S_CLKT 0x00000200 |
#define BCM2835_BSC_S_RXD 0x00000020 |
#define BCM2835_BSC_S_RXF 0x00000080 |
#define BCM2835_BSC_S_RXR 0x00000008 |
#define BCM2835_BSC_S_TXD 0x00000010 |
#define BCM2835_BSC_S_TXE 0x00000040 |
#define BCM2835_BSC_S_TXW 0x00000004 |
#define BCM2835_CLOCK_BASE 0x101000 |
#define BCM2835_CORE_CLK_HZ 250000000 |
#define BCM2835_GPAFEN0 0x0088 |
#define BCM2835_GPAFEN1 0x008c |
#define BCM2835_GPAREN0 0x007c |
#define BCM2835_GPAREN1 0x0080 |
#define BCM2835_GPEDS0 0x0040 |
#define BCM2835_GPEDS1 0x0044 |
#define BCM2835_GPFEN0 0x0058 |
#define BCM2835_GPFEN1 0x005c |
#define BCM2835_GPFSEL0 0x0000 |
#define BCM2835_GPHEN0 0x0064 |
#define BCM2835_GPHEN1 0x0068 |
#define BCM2835_GPIO_BASE 0x200000 |
#define BCM2835_GPIO_PADS 0x100000 |
#define BCM2835_GPIO_PWM 0x20C000 |
#define BCM2835_GPLEN0 0x0070 |
#define BCM2835_GPLEN1 0x0074 |
#define BCM2835_GPPUDCLK0 0x0098 |
#define BCM2835_GPPUDCLK1 0x009c |
#define BCM2835_GPREN0 0x004c |
#define BCM2835_GPREN1 0x0050 |
#define BCM2835_PAD_HYSTERESIS_ENABLED 0x08 |
#define BCM2835_PAD_PASSWRD (0x5A << 24) |
#define BCM2835_PAD_SLEW_RATE_UNLIMITED 0x10 |
#define BCM2835_PADS_GPIO_0_27 0x002c |
#define BCM2835_PADS_GPIO_28_45 0x0030 |
#define BCM2835_PADS_GPIO_46_53 0x0034 |
#define BCM2835_PAGE_SIZE (4*1024) |
#define BCM2835_PERI_BASE 0x20000000 |
Physical addresses for various peripheral register sets Base Physical Address of the BCM 2835 peripheral registers Note this is different for the RPi2 BCM2836, where this is derived from /proc/device-tree/soc/ranges If /proc/device-tree/soc/ranges exists on a RPi 1 OS, it would be expected to contain the following numbers:
Peripherals block base address on RPi 1
#define BCM2835_PERI_SIZE 0x01000000 |
#define BCM2835_RPI2_PERI_BASE 0x3F000000 |
#define BCM2835_RPI4_PERI_BASE 0xFE000000 |
#define BCM2835_RPI4_PERI_SIZE 0x01800000 |
#define BCM2835_SPI0_BASE 0x204000 |
#define BCM2835_SPI0_CS 0x0000 |
#define BCM2835_SPI0_CS_ADCS 0x00000800 |
#define BCM2835_SPI0_CS_CLEAR 0x00000030 |
#define BCM2835_SPI0_CS_CLEAR_RX 0x00000020 |
#define BCM2835_SPI0_CS_CLEAR_TX 0x00000010 |
#define BCM2835_SPI0_CS_CSPOL 0x00000040 |
#define BCM2835_SPI0_CS_CSPOL0 0x00200000 |
#define BCM2835_SPI0_CS_CSPOL1 0x00400000 |
#define BCM2835_SPI0_CS_CSPOL2 0x00800000 |
#define BCM2835_SPI0_CS_DMA_LEN 0x01000000 |
#define BCM2835_SPI0_CS_DONE 0x00010000 |
#define BCM2835_SPI0_CS_INTD 0x00000200 |
#define BCM2835_SPI0_CS_INTR 0x00000400 |
#define BCM2835_SPI0_CS_LEN_LONG 0x02000000 |
#define BCM2835_SPI0_CS_RXD 0x00020000 |
#define BCM2835_SPI0_CS_RXR 0x00080000 |
#define BCM2835_SPI0_CS_TXD 0x00040000 |
#define BCM2835_SPI0_FIFO 0x0004 |
#define BCM2835_SPI1_BASE 0x215080 |
#define BCM2835_SPI2_BASE 0x2150C0 |
#define BCM2835_ST_BASE 0x3000 |
#define BCM2835_ST_CHI 0x0008 |
#define BCM2835_ST_CLO 0x0004 |
#define BMC2835_RPI2_DT_FILENAME "/proc/device-tree/soc/ranges" |
#define HIGH 0x1 |
#define LOW 0x0 |
#define MIN | ( | a, | |
b | |||
) | (a < b ? a : b) |
bcm2835PortFunction Port function select modes for bcm2835_gpio_fsel()
bcm2835I2CClockDivider Specifies the divider used to generate the I2C clock from the system clock. Clock divided is based on nominal base clock rate of 250MHz
bcm2835I2CReasonCodes Specifies the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions.
enum bcm2835PadGroup |
bcm2835PadGroup Pad group specification for bcm2835_gpio_pad()
Enumerator | |
---|---|
BCM2835_PAD_GROUP_GPIO_0_27 | Pad group for GPIO pads 0 to 27 |
BCM2835_PAD_GROUP_GPIO_28_45 | Pad group for GPIO pads 28 to 45 |
BCM2835_PAD_GROUP_GPIO_46_53 | Pad group for GPIO pads 46 to 53 |
enum bcm2835PUDControl |
bcm2835PUDControl Pullup/Pulldown defines for bcm2835_gpio_pud()
Enumerator | |
---|---|
BCM2835_GPIO_PUD_OFF | Off ? disable pull-up/down 0b00 |
BCM2835_GPIO_PUD_DOWN | Enable Pull Down control 0b01 |
BCM2835_GPIO_PUD_UP | Enable Pull Up control 0b10 |
enum bcm2835RegisterBase |
bcm2835RegisterBase Register bases for bcm2835_regbase()
enum bcm2835SPIBitOrder |
bcm2835SPIBitOrder SPI Bit order Specifies the SPI data bit ordering for bcm2835_spi_setBitOrder()
Enumerator | |
---|---|
BCM2835_SPI_BIT_ORDER_LSBFIRST | LSB First |
BCM2835_SPI_BIT_ORDER_MSBFIRST | MSB First |
enum bcm2835SPIChipSelect |
bcm2835SPIClockDivider Specifies the divider used to generate the SPI clock from the system clock. Figures below give the divider, clock period and clock frequency. Clock divided is based on nominal core clock rate of 250MHz on RPi1 and RPi2, and 400MHz on RPi3. It is reported that (contrary to the documentation) any even divider may used. The frequencies shown for each divider have been confirmed by measurement on RPi1 and RPi2. The system clock frequency on RPi3 is different, so the frequency you get from a given divider will be different. See comments in 'SPI Pins' for information about reliable SPI speeds. Note: it is possible to change the core clock rate of the RPi 3 back to 250MHz, by putting
in the config.txt
enum bcm2835SPIMode |
SPI Data mode Specify the SPI data mode to be passed to bcm2835_spi_setDataMode()
Enumerator | |
---|---|
BCM2835_SPI_MODE0 | CPOL = 0, CPHA = 0 |
BCM2835_SPI_MODE1 | CPOL = 0, CPHA = 1 |
BCM2835_SPI_MODE2 | CPOL = 1, CPHA = 0 |
BCM2835_SPI_MODE3 | CPOL = 1, CPHA = 1 |
enum RPiGPIOPin |
GPIO Pin Numbers.
Here we define Raspberry Pin GPIO pins on P1 in terms of the underlying BCM GPIO pin numbers. These can be passed as a pin number to any function requiring a pin. Not all pins on the RPi 26 bin IDE plug are connected to GPIO pins and some can adopt an alternate function. RPi version 2 has some slightly different pinouts, and these are values RPI_V2_*. RPi B+ has yet differnet pinouts and these are defined in RPI_BPLUS_*. At bootup, pins 8 and 10 are set to UART0_TXD, UART0_RXD (ie the alt0 function) respectively When SPI0 is in use (ie after bcm2835_spi_begin()), SPI0 pins are dedicated to SPI and cant be controlled independently. If you are using the RPi Compute Module, just use the GPIO number: there is no need to use one of these symbolic names
volatile uint32_t* bcm2835_aux |
Base of the AUX registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_bsc0 |
Base of the BSC0 registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_bsc1 |
Base of the BSC1 registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_clk |
Base of the CLK registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_gpio |
Base of the GPIO registers. Available after bcm2835_init has been called
volatile uint32_t* bcm2835_pads |
Base of the PADS registers. Available after bcm2835_init has been called (as root)
uint32_t* bcm2835_peripherals |
Virtual memory address of the mapped peripherals block
uint32_t* bcm2835_peripherals_base |
Physical address and size of the peripherals block May be overridden on RPi2
uint32_t bcm2835_peripherals_size |
Size of the peripherals block to be mapped
volatile uint32_t* bcm2835_pwm |
Base of the PWM registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_spi0 |
Base of the SPI0 registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_spi1 |
Base of the SPI1 registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_st |
Base of the ST (System Timer) registers. Available after bcm2835_init has been called (as root)